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| author | John Crispin <blogic@openwrt.org> | 2015-11-04 13:14:13 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 08:38:18 +0100 |
| commit | 1601078df26605da7a8107bdd3143ef6b9d07e3b (patch) | |
| tree | 6928ac56cd3946185cc4f793202fe3560138ec01 /arch/mips/lantiq | |
| parent | MIPS: ralink: Add missing clock on rt305x (diff) | |
| download | linux-1601078df26605da7a8107bdd3143ef6b9d07e3b.tar.xz linux-1601078df26605da7a8107bdd3143ef6b9d07e3b.zip | |
MIPS: lantiq: Return correct value for fpi clock on ar9
Some configurations of AR9 reported the incorrect speed for the fpi bus.
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11448/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lantiq')
| -rw-r--r-- | arch/mips/lantiq/xway/clk.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c index 80aad3080ef8..07f6d5b0b65e 100644 --- a/arch/mips/lantiq/xway/clk.c +++ b/arch/mips/lantiq/xway/clk.c @@ -88,8 +88,9 @@ unsigned long ltq_ar9_fpi_hz(void) unsigned long sys = ltq_ar9_sys_hz(); if (ltq_cgu_r32(CGU_SYS) & BIT(0)) - return sys; - return sys >> 1; + return sys / 3; + else + return sys / 2; } unsigned long ltq_ar9_cpu_hz(void) |