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| author | James Hogan <james.hogan@imgtec.com> | 2015-05-19 10:50:36 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-06-21 21:52:36 +0200 |
| commit | decebccd76e4da9bb096962c230b6ed740606e49 (patch) | |
| tree | 28c00bcd0620525b43689728f88bdfa0a4a41f8f /arch/mips/lib | |
| parent | MIPS: dump_tlb: Take global bit into account (diff) | |
| download | linux-decebccd76e4da9bb096962c230b6ed740606e49.tar.xz linux-decebccd76e4da9bb096962c230b6ed740606e49.zip | |
MIPS: dump_tlb: Take EHINV bit into account
The EHINV bit in EntryHi allows a TLB entry to be properly marked
invalid so that EntryHi doesn't have to be set to a unique value to
avoid machine check exceptions due to multiple matching entries.
Unfortunately dump_tlb() doesn't take this into account so it will print
all the uninteresting invalid TLB entries if the current ASID happens to
be 00. Therefore add a condition to skip entries which are marked
invalid with the EHINV bit.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10076/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lib')
| -rw-r--r-- | arch/mips/lib/dump_tlb.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 995c393e3342..3bcdd53c832f 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -67,6 +67,9 @@ static void dump_tlb(int first, int last) entrylo0 = read_c0_entrylo0(); entrylo1 = read_c0_entrylo1(); + /* EHINV bit marks entire entry as invalid */ + if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV) + continue; /* * Prior to tlbinv, unused entries have a virtual address of * CKSEG0. |