diff options
| author | Huacai Chen <chenhc@lemote.com> | 2020-06-17 14:34:42 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-07-08 11:15:53 +0200 |
| commit | 04ef32aff23911006db97d3814290097327a2160 (patch) | |
| tree | d5d653a7eca8c03249f84a7679d6495890709c94 /arch/mips/loongson64/cpucfg-emul.c | |
| parent | dt-bindings: MIPS: Fix tabs in Ingenic SoCs binding. (diff) | |
| download | linux-04ef32aff23911006db97d3814290097327a2160.tar.xz linux-04ef32aff23911006db97d3814290097327a2160.zip | |
MIPS: Unify naming style of vendor CP0.Config6 bits
Other vendor-defined registers use the vendor name as a prefix, not an
infix, so unify the naming style of CP0.Config6 bits.
Suggested-by: Maciej W. Rozycki" <macro@linux-mips.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/loongson64/cpucfg-emul.c')
| -rw-r--r-- | arch/mips/loongson64/cpucfg-emul.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c index cd619b47ba1f..630927e46d3b 100644 --- a/arch/mips/loongson64/cpucfg-emul.c +++ b/arch/mips/loongson64/cpucfg-emul.c @@ -57,11 +57,11 @@ static void decode_loongson_config6(struct cpuinfo_mips *c) { u32 config6 = read_c0_config6(); - if (config6 & MIPS_CONF6_LOONGSON_SFBEN) + if (config6 & LOONGSON_CONF6_SFBEN) c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP; - if (config6 & MIPS_CONF6_LOONGSON_LLEXC) + if (config6 & LOONGSON_CONF6_LLEXC) c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC; - if (config6 & MIPS_CONF6_LOONGSON_SCRAND) + if (config6 & LOONGSON_CONF6_SCRAND) c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND; } |