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author | Ralf Baechle <ralf@linux-mips.org> | 2009-06-19 16:01:44 +0200 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-24 19:34:39 +0200 |
commit | 44eeab67416711db9b84610ef18c99a60415dff8 (patch) | |
tree | e9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09 /arch/mips/mipssim/sim_time.c | |
parent | MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users. (diff) | |
download | linux-44eeab67416711db9b84610ef18c99a60415dff8.tar.xz linux-44eeab67416711db9b84610ef18c99a60415dff8.zip |
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled. A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled. A local
flush is not needed either because we didn't change any mappings. So
just delete the code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mipssim/sim_time.c')
0 files changed, 0 insertions, 0 deletions