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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-24 19:47:38 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-24 19:47:38 +0200 |
| commit | c82e6d450fda56cb2d4f68534173d3cd11b32f9f (patch) | |
| tree | bac06ba3b1134e5eab072476129e943a1bf04fa6 /arch/mips/mipssim/sim_time.c | |
| parent | Merge git://git.kernel.org/pub/scm/linux/kernel/git/agk/linux-2.6-dm (diff) | |
| parent | Staging: octeon-ethernet: Fix race freeing transmit buffers. (diff) | |
| download | linux-c82e6d450fda56cb2d4f68534173d3cd11b32f9f.tar.xz linux-c82e6d450fda56cb2d4f68534173d3cd11b32f9f.zip | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
Staging: octeon-ethernet: Fix race freeing transmit buffers.
Staging: octeon-ethernet: Convert to use net_device_ops.
MIPS: Cavium: Add CPU hotplugging code.
MIPS: SMP: Allow suspend and hibernation if CPU hotplug is available
MIPS: Add arch generic CPU hotplug
DMA: txx9dmac: use dma_unmap_single if DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE set
MIPS: Sibyte: Fix build error if CONFIG_SERIAL_SB1250_DUART is undefined.
MIPS: MIPSsim: Fix build error if MSC01E_INT_BASE is undefined.
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.
MIPS: bug.h Build fix - include <linux/compiler.h>.
Diffstat (limited to 'arch/mips/mipssim/sim_time.c')
| -rw-r--r-- | arch/mips/mipssim/sim_time.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index 881ecbc1fa23..0cea932f1241 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -91,6 +91,7 @@ unsigned __cpuinit get_c0_compare_int(void) mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; } else { #endif + { if (cpu_has_vint) set_vi_handler(cp0_compare_irq, mips_timer_dispatch); mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |