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| author | Paul Burton <paul.burton@imgtec.com> | 2017-06-02 21:39:04 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-06-28 12:22:39 +0200 |
| commit | 859aeb1b0dd1b9c6ff3d78f6cb913a73af9da247 (patch) | |
| tree | f3d28bf9dc8fe6a93c431f3091c3cc5c6f616e3e /arch/mips/mm/c-r4k.c | |
| parent | MIPS: Perform post-DMA cache flushes on systems with MAARs (diff) | |
| download | linux-859aeb1b0dd1b9c6ff3d78f6cb913a73af9da247.tar.xz linux-859aeb1b0dd1b9c6ff3d78f6cb913a73af9da247.zip | |
MIPS: Probe the I6500 CPU
Introduce the I6500 PRID & probe it just the same way as I6400. The MIPS
I6500 is the latest in Imagination Technologies' I-Class range of CPUs,
with a focus on scalability & heterogeneity. It introduces the notion of
multiple clusters to the MIPS Coherent Processing System, allowing for a
far higher total number of cores & threads in a system when compared
with its predecessors. Clusters don't need to be identical, and may
contain differing numbers of cores & IOCUs, or cores with differing
properties.
This patch alone adds the basic support for booting Linux on an I6500
CPU without support for any of its new functionality, for which support
will be introduced in further patches.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16190/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 3fe99cb271a9..81d6a15c93d0 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1453,6 +1453,7 @@ static void probe_pcache(void) case CPU_20KC: case CPU_25KF: case CPU_I6400: + case CPU_I6500: case CPU_SB1: case CPU_SB1A: case CPU_XLR: @@ -1512,6 +1513,7 @@ static void probe_pcache(void) case CPU_ALCHEMY: case CPU_I6400: + case CPU_I6500: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; |