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| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-01-15 11:28:29 +0100 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 16:37:31 +0100 |
| commit | b5ad2c21934951bbf6aadd8adbdd9889baad0ac0 (patch) | |
| tree | 23c9d24715f1e3f8da4936f41fccb4217cb5a0d1 /arch/mips/mm/c-r4k.c | |
| parent | MIPS: mm: c-r4k: Set the correct ISA level (diff) | |
| download | linux-b5ad2c21934951bbf6aadd8adbdd9889baad0ac0.tar.xz linux-b5ad2c21934951bbf6aadd8adbdd9889baad0ac0.zip | |
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 7ecee761ae2d..3f8059602765 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1473,7 +1473,8 @@ static void setup_scache(void) default: if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | - MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { + MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | + MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { #ifdef CONFIG_MIPS_CPU_SCACHE if (mips_sc_init ()) { scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; |