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| author | Arnd Bergmann <arnd@arndb.de> | 2013-05-06 23:38:00 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-05-06 23:38:00 +0200 |
| commit | 4183bef2e093a2f0aab45f2d5fed82b0e02aeacf (patch) | |
| tree | e84c484db3746a0f3ead0fb7a2bb9e5a42b89e85 /arch/mips/mm/c-r4k.c | |
| parent | ARM: dts: add mshc controller node for Exynos4x12 SoCs (diff) | |
| parent | Merge tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/pub/scm/linux/ke... (diff) | |
| download | linux-4183bef2e093a2f0aab45f2d5fed82b0e02aeacf.tar.xz linux-4183bef2e093a2f0aab45f2d5fed82b0e02aeacf.zip | |
Merge branch 'late/dt' into next/dt2
This is support for the ARM Chromebook, originally scheduled
as a "late" pull request. Since it's already late now, we
can combine this into the existing next/dt2 branch.
* late/dt:
ARM: exynos: dts: cros5250: add EC device
ARM: dts: Add sbs-battery for exynos5250-snow
ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
ARM: dts: Add chip-id controller node on Exynos4/5 SoC
ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index ecca559b8d7b..2078915eacb9 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void) return; default: - if (c->isa_level == MIPS_CPU_ISA_M32R1 || - c->isa_level == MIPS_CPU_ISA_M32R2 || - c->isa_level == MIPS_CPU_ISA_M64R1 || - c->isa_level == MIPS_CPU_ISA_M64R2) { + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { #ifdef CONFIG_MIPS_CPU_SCACHE if (mips_sc_init ()) { scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; |