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| author | Steven J. Hill <Steven.Hill@imgtec.com> | 2013-03-25 19:47:29 +0100 |
|---|---|---|
| committer | Steven J. Hill <Steven.Hill@imgtec.com> | 2013-05-01 23:32:49 +0200 |
| commit | b6d92b4a6bdb880b39789c677b952c53a437028d (patch) | |
| tree | f14d30f02314d75860aa1ed12449410e6659513b /arch/mips/mm/c-r4k.c | |
| parent | MIPS: malta: Add new Malta config files. (diff) | |
| download | linux-b6d92b4a6bdb880b39789c677b952c53a437028d.tar.xz linux-b6d92b4a6bdb880b39789c677b952c53a437028d.zip | |
MIPS: Add option to disable software I/O coherency.
Some MIPS controllers have hardware I/O coherency. This patch
detects those and turns off software coherency. A new kernel
command line option also allows the user to manually turn
software coherency on or off.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 2078915eacb9..f5943ab44987 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -33,6 +33,7 @@ #include <asm/war.h> #include <asm/cacheflush.h> /* for run_uncached() */ #include <asm/traps.h> +#include <asm/dma-coherence.h> /* * Special Variant of smp_call_function for use by cache functions: @@ -1377,20 +1378,6 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; - -static int __init setcoherentio(char *str) -{ - coherentio = 1; - - return 0; -} - -early_param("coherentio", setcoherentio); -#endif - static void __cpuinit r4k_cache_error_setup(void) { extern char __weak except_vec2_generic; @@ -1472,9 +1459,14 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* + * We want to run CMP kernels on core with and without coherent + * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether + * or not to flush caches. + */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); board_cache_error_setup = r4k_cache_error_setup; } |