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| author | James Hogan <james.hogan@imgtec.com> | 2016-01-22 11:58:26 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-09 12:00:03 +0200 |
| commit | 47f2ac5058a19cbbe70bbccba13d104c60b35bff (patch) | |
| tree | eeabe668aba9b404d9a0a383ba3461e748a9e1a2 /arch/mips/mm/c-r4k.c | |
| parent | MIPS: c-r4k: Sync icache when it fills from dcache (diff) | |
| download | linux-47f2ac5058a19cbbe70bbccba13d104c60b35bff.tar.xz linux-47f2ac5058a19cbbe70bbccba13d104c60b35bff.zip | |
MIPS: I6400: Icache fills from dcache
Coherence Manager 3 (CM3) as present in I6400 can fill icache lines
effectively from dirty dcaches, so there is no need to flush dirty lines
from dcaches through to L2 prior to icache invalidation.
Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc
evaluates to true, which avoids those dcache flushes.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index fc7289dfaf5a..69e7e5873af3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1311,6 +1311,7 @@ static void probe_pcache(void) break; case CPU_ALCHEMY: + case CPU_I6400: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; |