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authorDavid Daney <ddaney@caviumnetworks.com>2008-12-12 00:33:27 +0100
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 10:57:22 +0100
commit47d979eca33f8df49bfead2d5efa23a70b413882 (patch)
treee70554c6042ba2acf5c01df8e15a572ebf6e60d3 /arch/mips/mm/cache.c
parentMIPS: Add Cavium OCTEON processor constants and CPU probe. (diff)
downloadlinux-47d979eca33f8df49bfead2d5efa23a70b413882.tar.xz
linux-47d979eca33f8df49bfead2d5efa23a70b413882.zip
MIPS: Hook Cavium OCTEON cache init into cache.c
Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/cache.c')
-rw-r--r--arch/mips/mm/cache.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1eb7c71e3d6a..98ad0a82c29e 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void)
tx39_cache_init();
}
+ if (cpu_has_octeon_cache) {
+ extern void __weak octeon_cache_init(void);
+
+ octeon_cache_init();
+ }
+
setup_protection_map();
}