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| author | Steven Whitehouse <swhiteho@redhat.com> | 2006-03-31 22:34:58 +0200 |
|---|---|---|
| committer | Steven Whitehouse <swhiteho@redhat.com> | 2006-03-31 22:34:58 +0200 |
| commit | 86579dd06deecfa6ac88d5e84e4d63c397cd6f6d (patch) | |
| tree | b4475d3ccde53015ad84a06e4e55e64591171b75 /arch/mips/mm/pg-r4k.c | |
| parent | [GFS2] Update ioctl() to new interface (diff) | |
| parent | [PATCH] splice exports (diff) | |
| download | linux-86579dd06deecfa6ac88d5e84e4d63c397cd6f6d.tar.xz linux-86579dd06deecfa6ac88d5e84e4d63c397cd6f6d.zip | |
Merge branch 'master'
Diffstat (limited to 'arch/mips/mm/pg-r4k.c')
| -rw-r--r-- | arch/mips/mm/pg-r4k.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index f51e180072e3..e4390dc3eb48 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -124,7 +124,7 @@ static inline void build_nop(void) static inline void build_src_pref(int advance) { - if (!(load_offset & (cpu_dcache_line_size() - 1))) { + if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) { union mips_instruction mi; mi.i_format.opcode = pref_op; @@ -166,7 +166,7 @@ static inline void build_load_reg(int reg) static inline void build_dst_pref(int advance) { - if (!(store_offset & (cpu_dcache_line_size() - 1))) { + if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) { union mips_instruction mi; mi.i_format.opcode = pref_op; @@ -340,6 +340,12 @@ void __init build_clear_page(void) if (cpu_has_prefetch) { switch (current_cpu_data.cputype) { + case CPU_TX49XX: + /* TX49 supports only Pref_Load */ + pref_offset_clear = 0; + pref_offset_copy = 0; + break; + case CPU_RM9000: /* * As a workaround for erratum G105 which make the |