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| author | David Daney <david.daney@cavium.com> | 2015-01-15 14:11:13 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-02-20 15:31:27 +0100 |
| commit | e3d0ead59f6c1167c817ea338dd9395d517940e1 (patch) | |
| tree | 66f0c4d5f1443b0415cfa4a4f3b420d175abbf24 /arch/mips/mm/uasm.c | |
| parent | MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h (diff) | |
| download | linux-e3d0ead59f6c1167c817ea338dd9395d517940e1.tar.xz linux-e3d0ead59f6c1167c817ea338dd9395d517940e1.zip | |
MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX
Make messages refer to all CN6XXX.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/uasm.c')
| -rw-r--r-- | arch/mips/mm/uasm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index f86d293463a6..319051c34343 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -341,7 +341,7 @@ I_u3u1u2(_ldx) void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, unsigned int c) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) + if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) /* * As per erratum Core-14449, replace prefetches 0-4, * 6-24 with 'pref 28'. |