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| author | Steven J. Hill <sjhill@mips.com> | 2012-07-12 19:21:31 +0200 |
|---|---|---|
| committer | Steven J. Hill <sjhill@mips.com> | 2012-09-13 22:43:53 +0200 |
| commit | e6de1a09a2f6a6825341e8463866553b77848ed6 (patch) | |
| tree | 473dbf84055f232628e0b37ecfd4d9244d500eb5 /arch/mips/mm/uasm.c | |
| parent | MIPS: Avoid pipeline stalls on some MIPS32R2 cores. (diff) | |
| download | linux-e6de1a09a2f6a6825341e8463866553b77848ed6.tar.xz linux-e6de1a09a2f6a6825341e8463866553b77848ed6.zip | |
MIPS: uasm: Add INS and EXT instructions.
These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'arch/mips/mm/uasm.c')
| -rw-r--r-- | arch/mips/mm/uasm.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 64a28e819064..39b891056227 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -63,11 +63,12 @@ enum opcode { insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, - insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld, - insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori, - insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, - insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp, - insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, + insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, + insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, + insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, + insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, + insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, + insn_xori, }; struct insn { @@ -115,6 +116,9 @@ static struct insn insn_table[] __uasminitdata = { { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, @@ -341,6 +345,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msbdu3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, d-1, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -394,6 +405,8 @@ I_u2u1u3(_drotr) I_u2u1u3(_drotr32) I_u3u1u2(_dsubu) I_0(_eret) +I_u2u1msbdu3(_ext) +I_u2u1msbu3(_ins) I_u1(_j) I_u1(_jal) I_u1(_jr) |