diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-15 17:35:45 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-16 19:23:49 +0200 |
| commit | 64bfca5cd8c40fa138ad5db2513e8bcf8bd54ebd (patch) | |
| tree | 08caa0c52a24744e52012f3ccab5325d97e425ee /arch/mips/mm | |
| parent | [MIPS] Fix aliasing bug in copy_user_highpage, take 2. (diff) | |
| download | linux-64bfca5cd8c40fa138ad5db2513e8bcf8bd54ebd.tar.xz linux-64bfca5cd8c40fa138ad5db2513e8bcf8bd54ebd.zip | |
[MIPS] Cache: Provide more information on cache policy on bootup.
This should help making bug reports for the gadzillion of cores with all
their configuration and synthesis options more useful.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 971f6c047b8a..d7088331fb0f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -983,11 +983,15 @@ static void __init probe_pcache(void) printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, - cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", + cpu_has_vtag_icache ? "VIVT" : "VIPT", way_string[c->icache.ways], c->icache.linesz); - printk("Primary data cache %ldkB, %s, linesize %d bytes.\n", - dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz); + printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", + dcache_size >> 10, way_string[c->dcache.ways], + (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", + (c->dcache.flags & MIPS_CACHE_ALIASES) ? + "cache aliases" : "no aliases", + c->dcache.linesz); } /* |