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| author | David Daney <ddaney@caviumnetworks.com> | 2010-12-28 03:07:56 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-01-18 19:30:23 +0100 |
| commit | bb3d68c30a00918d4c9fa02a5c17a5aacf597977 (patch) | |
| tree | 6d6db066452de4a2ec28f24bc7b0c287eabd9967 /arch/mips/mm | |
| parent | MIPS: Use BBIT instructions in TLB handlers (diff) | |
| download | linux-bb3d68c30a00918d4c9fa02a5c17a5aacf597977.tar.xz linux-bb3d68c30a00918d4c9fa02a5c17a5aacf597977.zip | |
MIPS: Add LDX and LWX instructions to uasm.
Needed by Octeon II optimized TLB handlers.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Pachwork: https://patchwork.linux-mips.org/patch/1903/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/uasm.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 99f0347e82d2..357916de0fab 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -68,7 +68,8 @@ enum opcode { insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, - insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1 + insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1, + insn_lwx, insn_ldx }; struct insn { @@ -146,6 +147,8 @@ static struct insn insn_table[] __uasminitdata = { { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, + { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, { insn_invalid, 0, 0 } }; @@ -434,6 +437,8 @@ I_u2u1msb32u3(_dinsm); I_u1(_syscall); I_u1u2s3(_bbit0); I_u1u2s3(_bbit1); +I_u3u1u2(_lwx) +I_u3u1u2(_ldx) #ifdef CONFIG_CPU_CAVIUM_OCTEON #include <asm/octeon/octeon.h> |