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author | Huang Pei <huangpei@loongson.cn> | 2021-03-13 02:39:27 +0100 |
---|---|---|
committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-03-14 14:08:15 +0100 |
commit | c6972fb9ba8aab384568665411015b7deb8a8609 (patch) | |
tree | 6c28cfd26d67e3e5f9b12368e7dad65b0702a8b7 /arch/mips/mm | |
parent | MIPS: ingenic: gcw0: SPI panel does not require active-high CS (diff) | |
download | linux-c6972fb9ba8aab384568665411015b7deb8a8609.tar.xz linux-c6972fb9ba8aab384568665411015b7deb8a8609.zip |
MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling
+. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of
0xa8xx_xxxx_xxxx_xxxx
+. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit
+. cast CAC_BASE into u64 to silence warning on MIPS32
CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field.
+. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53,
only save 53 - 12 = 41 bits, aka :
bit[63:59] | 0000 00 | bit[53:12] | 0000 0000 0000
+. for CKSEG0, only save 29 - 12 = 17 bits
when switching pgd, only need to save bit[53:12] or bit[28:12] into
CP0 Context's bit[63:23], see folling asm generated at run time
tlbmiss_handler_setup_pgd:
.set push
.set noreorder
dsra a2, a0, 29
move a3, a0
dins a0, zero, 29, 35
daddiu a2, a2, 4 //for CKSEG0, a2 from 0xfffffffffffffffc
//into 0
movn a0, a3, a2
dsll a0, a0, 11
jr ra
dmtc0 a0, CP0_CONTEXT
.set pop
when using it on page walking
dmfc0 k0, CP0_CONTEXT
dins k0, zero, 0, 23 // zero badv2
ori k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59]
drotr k0, k0, 11 // kick it in the right place
Signed-off-by: Huang Pei <huangpei@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/tlbex.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 0fb1db8a8ef7..cd4afcdf3725 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -849,8 +849,8 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* Clear lower 23 bits of context. */ uasm_i_dins(p, ptr, 0, 0, 23); - /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_ori(p, ptr, ptr, 0x540); + /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ + uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); uasm_i_drotr(p, ptr, ptr, 11); #elif defined(CONFIG_SMP) UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); @@ -1165,8 +1165,9 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, if (pgd_reg == -1) { vmalloc_branch_delay_filled = 1; - /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_ori(p, ptr, ptr, 0x540); + /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ + uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); + uasm_i_drotr(p, ptr, ptr, 11); } |