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| author | Paul Burton <paul.burton@imgtec.com> | 2013-12-24 04:50:35 +0100 |
|---|---|---|
| committer | Paul Burton <paul.burton@imgtec.com> | 2014-05-28 17:20:27 +0200 |
| commit | 53ed138986e1022c2b6fef7f8e9731f5bf3e6af1 (patch) | |
| tree | b18132ab7697d3d2acf01c8b059fa91939a8e9c1 /arch/mips/mm | |
| parent | MIPS: uasm: add sync instruction (diff) | |
| download | linux-53ed138986e1022c2b6fef7f8e9731f5bf3e6af1.tar.xz linux-53ed138986e1022c2b6fef7f8e9731f5bf3e6af1.zip | |
MIPS: uasm: add wait instruction
This patch allows use of the wait instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/uasm-micromips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm-mips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm.c | 3 |
3 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c index 9500f2a951f9..bcbcf4ae69b7 100644 --- a/arch/mips/mm/uasm-micromips.c +++ b/arch/mips/mm/uasm-micromips.c @@ -104,6 +104,7 @@ static struct insn insn_table_MM[] = { { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, + { insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM }, { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, { insn_dins, 0, 0 }, diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index 51063fdcefbf..c69f785753b5 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -113,6 +113,7 @@ static struct insn insn_table[] = { { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, + { insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM }, { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, { insn_invalid, 0, 0 } diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 7c1380127a82..46d2173e6f24 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -54,7 +54,7 @@ enum opcode { insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, - insn_xor, insn_xori, + insn_wait, insn_xor, insn_xori, }; struct insn { @@ -276,6 +276,7 @@ I_0(_tlbp) I_0(_tlbr) I_0(_tlbwi) I_0(_tlbwr) +I_u1(_wait); I_u3u1u2(_xor) I_u2u1u3(_xori) I_u2u1msbu3(_dins); |