diff options
| author | Chris Dearman <chris@mips.com> | 2007-09-19 01:46:32 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 18:14:25 +0200 |
| commit | 962f480e0f9024ecdcfe2ba1d216c038ee328ced (patch) | |
| tree | 7bdc4f14bd9e894ed3178b3a9b6ec235710868a6 /arch/mips/mm | |
| parent | [MIPS] Remove TLB sanitation code (diff) | |
| download | linux-962f480e0f9024ecdcfe2ba1d216c038ee328ced.tar.xz linux-962f480e0f9024ecdcfe2ba1d216c038ee328ced.zip | |
[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/init.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/tlb-r4k.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index c7aed133d11d..235833af3a8b 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -142,7 +142,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) #endif vaddr = __fix_to_virt(FIX_CMAP_END - idx); pte = mk_pte(page, PAGE_KERNEL); -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) entrylo = pte.pte_high; #else entrylo = pte_val(pte) >> 6; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 63065d6e8063..5ce2fa745626 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -299,7 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) write_c0_entrylo0(ptep->pte_high); ptep++; write_c0_entrylo1(ptep->pte_high); |