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| author | James Morris <jmorris@macbook.(none)> | 2009-12-03 07:33:40 +0100 |
|---|---|---|
| committer | James Morris <jmorris@macbook.(none)> | 2009-12-03 07:33:40 +0100 |
| commit | c84d6efd363a3948eb32ec40d46bab6338580454 (patch) | |
| tree | 3ba7ac46e6626fe8ac843834588609eb6ccee5c6 /arch/mips/mti-malta/malta-pci.c | |
| parent | TOMOYO: Add recursive directory matching operator support. (diff) | |
| parent | Linux 2.6.32 (diff) | |
| download | linux-c84d6efd363a3948eb32ec40d46bab6338580454.tar.xz linux-c84d6efd363a3948eb32ec40d46bab6338580454.zip | |
Merge branch 'master' into next
Diffstat (limited to 'arch/mips/mti-malta/malta-pci.c')
| -rw-r--r-- | arch/mips/mti-malta/malta-pci.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b9743190609a..2fbfa1a8c3a9 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -27,7 +27,7 @@ #include <linux/init.h> #include <asm/gt64120.h> - +#include <asm/gcmpregs.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/bonito64.h> #include <asm/mips-boards/msc01_pci.h> @@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(0, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); @@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(1, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif /* If ranges overlap I/O takes precedence. */ start = start & mask; end = start | ~mask; @@ -241,3 +249,16 @@ void __init mips_pcibios_init(void) register_pci_controller(controller); } + +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); |