diff options
| author | Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> | 2013-10-08 17:17:48 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-10-29 21:18:23 +0100 |
| commit | 7f081f175502373673c015a4d0fa1d5cc264758a (patch) | |
| tree | bd53f2a1470b37b79d7e5f5f6e0fe7bcfbc452d4 /arch/mips/mti-malta | |
| parent | Linux 3.12-rc7 (diff) | |
| download | linux-7f081f175502373673c015a4d0fa1d5cc264758a.tar.xz linux-7f081f175502373673c015a4d0fa1d5cc264758a.zip | |
MIPS: Perf: Fix 74K cache map
According to Software User's Manual, the event of last-level-cache
read/write misses is mapped to even counters. Odd counters of that
event number count miss cycles.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6036/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-malta')
0 files changed, 0 insertions, 0 deletions