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authorTim Anderson <tanderson@mvista.com>2009-06-18 01:22:53 +0200
committerRalf Baechle <ralf@linux-mips.org>2009-07-03 16:45:26 +0200
commit0365070f05f12f1648b4adf22cfb52ec7a8a371c (patch)
tree029bce65da52745722a473bf663e861157a686a9 /arch/mips/mti-malta
parentMIPS: CMP: Extend IPI handling to CPU number (diff)
downloadlinux-0365070f05f12f1648b4adf22cfb52ec7a8a371c.tar.xz
linux-0365070f05f12f1648b4adf22cfb52ec7a8a371c.zip
MIPS: CMP: activate CMP support
Most of the CMP support was added before, this mostly correct compile problems but adds a platform specific translation for the interrupt number based on cpu number. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-malta')
-rw-r--r--arch/mips/mti-malta/malta-int.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 4e14972dcfc4..bc0ba58acfd5 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -336,6 +336,16 @@ static int gic_resched_int_base;
static int gic_call_int_base;
#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
+
+unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
+{
+ return GIC_CALL_INT(cpu);
+}
+
+unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
+{
+ return GIC_RESCHED_INT(cpu);
+}
#endif /* CONFIG_MIPS_MT_SMP */
static struct irqaction i8259irq = {