diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2008-06-12 18:26:02 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-06-16 16:14:47 +0200 |
| commit | 89052bd7b393434f7c573ce6a3b88c5f143586d2 (patch) | |
| tree | e68bf4c2b46ca1c33b0fa1b78da6ea2a4db3aff4 /arch/mips/nxp | |
| parent | [MIPS] Add RM200 with R5000 CPU to known ARC machines (diff) | |
| download | linux-89052bd7b393434f7c573ce6a3b88c5f143586d2.tar.xz linux-89052bd7b393434f7c573ce6a3b88c5f143586d2.zip | |
[MIPS] Fix build for PNX platforms.
Build error was caused by commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/nxp')
| -rw-r--r-- | arch/mips/nxp/pnx8550/jbs/board_setup.c | 11 | ||||
| -rw-r--r-- | arch/mips/nxp/pnx8550/stb810/board_setup.c | 10 |
2 files changed, 2 insertions, 19 deletions
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c index f92826e0096d..57dd903ca408 100644 --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c @@ -47,16 +47,7 @@ void __init board_setup(void) { - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); - BARRIER; + unsigned long configpr; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c index 1282c27cfcb7..af2a55e0b4e9 100644 --- a/arch/mips/nxp/pnx8550/stb810/board_setup.c +++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c @@ -33,15 +33,7 @@ void __init board_setup(void) { - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); + unsigned long configpr; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ |