diff options
| author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-02-01 21:18:59 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 20:30:20 +0200 |
| commit | aa0980b8090878bf42bc73a13d051a203a201d7d (patch) | |
| tree | c4e411d4100a6006b0bc2945742b0ab2fa10b2e5 /arch/mips/pci/ops-msc.c | |
| parent | Actually route cPCI interrupts. Update inaccurate comments. (diff) | |
| download | linux-aa0980b8090878bf42bc73a13d051a203a201d7d.tar.xz linux-aa0980b8090878bf42bc73a13d051a203a201d7d.zip | |
Fixes for system controllers for Atlas/Malta core cards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/ops-msc.c')
| -rw-r--r-- | arch/mips/pci/ops-msc.c | 31 |
1 files changed, 5 insertions, 26 deletions
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c index 7bc099643a9d..5d9fbb0f4670 100644 --- a/arch/mips/pci/ops-msc.c +++ b/arch/mips/pci/ops-msc.c @@ -21,7 +21,6 @@ * MIPS boards specific PCI support. * */ -#include <linux/config.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/kernel.h> @@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 * data) { unsigned char busnum = bus->number; - unsigned char type; u32 intr; -#ifdef CONFIG_MIPS_BOARDS_GEN - if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) { - /* MIPS Core boards have SOCit connected as device 17 */ - return -1; - } -#endif - /* Clear status register bits. */ MSC_WRITE(MSC01_PCI_INTSTAT, (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); - /* Setup address */ - if (busnum == 0) - type = 0; /* Type 0 */ - else - type = 1; /* Type 1 */ - MSC_WRITE(MSC01_PCI_CFGADDR, ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | - (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) - | (PCI_FUNC(devfn) << - MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / - 4) << - MSC01_PCI_CFGADDR_RNUM_SHF) - | (type))); + (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) | + (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) | + ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF))); /* Perform access */ if (access_type == PCI_ACCESS_WRITE) @@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type, /* Detect Master/Target abort */ MSC_READ(MSC01_PCI_INTSTAT, intr); - if (intr & (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)) { + if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) { /* Error occurred */ /* Clear bits */ - MSC_READ(MSC01_PCI_INTSTAT, intr); MSC_WRITE(MSC01_PCI_INTSTAT, - (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)); + (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); return -1; } |