diff options
| author | Jonas Gorski <jonas.gorski@gmail.com> | 2012-10-28 12:49:53 +0100 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-11-09 11:37:17 +0100 |
| commit | f2d1035e956052d29c83fe8f8da0d056af6d221a (patch) | |
| tree | 1cb6769113f52ebf6e4457b6ec0adc38e7886e0b /arch/mips/pci/pci-bcm63xx.c | |
| parent | MIPS: BCM47xx: sprom: read values without prefix as fallback (diff) | |
| download | linux-f2d1035e956052d29c83fe8f8da0d056af6d221a.tar.xz linux-f2d1035e956052d29c83fe8f8da0d056af6d221a.zip | |
MIPS: BCM63XX: add and use a clock for PCIe
Add a PCIe clock and use that instead of directly touching the clock
control register. While at it, fail if there is no such clock.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Acked-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4452
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/pci/pci-bcm63xx.c')
| -rw-r--r-- | arch/mips/pci/pci-bcm63xx.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c index 8a48139d219c..fa8c320936fe 100644 --- a/arch/mips/pci/pci-bcm63xx.c +++ b/arch/mips/pci/pci-bcm63xx.c @@ -11,6 +11,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/delay.h> +#include <linux/clk.h> #include <asm/bootinfo.h> #include "pci-bcm63xx.h" @@ -119,11 +120,6 @@ static void __init bcm63xx_reset_pcie(void) { u32 val; - /* enable clock */ - val = bcm_perf_readl(PERF_CKCTL_REG); - val |= CKCTL_6328_PCIE_EN; - bcm_perf_writel(val, PERF_CKCTL_REG); - /* enable SERDES */ val = bcm_misc_readl(MISC_SERDES_CTRL_REG); val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; @@ -150,10 +146,19 @@ static void __init bcm63xx_reset_pcie(void) mdelay(200); } +static struct clk *pcie_clk; + static int __init bcm63xx_register_pcie(void) { u32 val; + /* enable clock */ + pcie_clk = clk_get(NULL, "pcie"); + if (IS_ERR_OR_NULL(pcie_clk)) + return -ENODEV; + + clk_prepare_enable(pcie_clk); + bcm63xx_reset_pcie(); /* configure the PCIe bridge */ |