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authorJim Quinlan <jim2101024@gmail.com>2013-08-27 22:57:51 +0200
committerRalf Baechle <ralf@linux-mips.org>2013-09-04 18:55:58 +0200
commitf86f55d3ad21b21b736bdeb29bee0f0937b77138 (patch)
treea6f3ff7f993e3bbacccd01d464e5c983094c76ca /arch/mips/pci/pci-octeon.c
parentMIPS: ralink: Add support for reset-controller API (diff)
downloadlinux-f86f55d3ad21b21b736bdeb29bee0f0937b77138.tar.xz
linux-f86f55d3ad21b21b736bdeb29bee0f0937b77138.zip
MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000
The BMIPS5000 (Zephyr) processor utilizes instruction speculation. A stale misprediction address in either the JTB or the CRS may trigger a prefetch inside a region that is currently being used by a DMA engine, which is not IO-coherent. This prefetch will fetch a line into the scache, and that line will soon become stale (ie wrong) during/after the DMA. Mayhem ensues. In dma-default.c, the r10000 is handled as a special case in the same way that we want to handle Zephyr. So we generalize the exception cases into a function, and include Zephyr as one of the processors that needs this special care. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5776/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/pci-octeon.c')
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