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| author | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 18:17:33 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 18:17:33 +0200 |
| commit | ade63aada79c61bcd5f51cbd310f237399892268 (patch) | |
| tree | 4f8605528bfd9b6261679883974b9ac4870223dd /arch/mips/pci | |
| parent | MIPS: CPC: Use __raw_ memory access functions (diff) | |
| parent | MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume() (diff) | |
| download | linux-ade63aada79c61bcd5f51cbd310f237399892268.tar.xz linux-ade63aada79c61bcd5f51cbd310f237399892268.zip | |
Merge branch '3.14-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/msi-octeon.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index d37be36dc659..2b91b0e61566 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -150,6 +150,7 @@ msi_irq_allocated: msg.address_lo = ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff; msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32; + break; case OCTEON_DMA_BAR_TYPE_BIG: /* When using big bar, Bar 0 is based at 0 */ msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff; |