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authorJohn Crispin <blogic@openwrt.org>2013-01-19 09:54:26 +0100
committerJohn Crispin <blogic@openwrt.org>2013-02-17 00:15:17 +0100
commitbae696a267d81ea268f4de1e396b8c82154f22ed (patch)
treea0d7b008010d7938c14039caefbac8df81e714bf /arch/mips/pci
parentMIPS: lantiq: add GPHY clock gate bits (diff)
downloadlinux-bae696a267d81ea268f4de1e396b8c82154f22ed.tar.xz
linux-bae696a267d81ea268f4de1e396b8c82154f22ed.zip
MIPS: lantiq: improve pci reset gpio handling
We need to make sure that the reset gpio is available and also set a sane default state. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4817/
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/pci-lantiq.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 95681789b51e..f32664bbbe17 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -129,8 +129,16 @@ static int ltq_pci_startup(struct platform_device *pdev)
/* setup reset gpio used by pci */
reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
- if (gpio_is_valid(reset_gpio))
- devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset");
+ if (gpio_is_valid(reset_gpio)) {
+ int ret = devm_gpio_request(&pdev->dev,
+ reset_gpio, "pci-reset");
+ if (ret) {
+ dev_err(&pdev->dev,
+ "failed to request gpio %d\n", reset_gpio);
+ return ret;
+ }
+ gpio_direction_output(reset_gpio, 1);
+ }
/* enable auto-switching between PCI and EBU */
ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);