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| author | John Crispin <blogic@openwrt.org> | 2016-01-04 20:24:01 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-01-20 00:39:20 +0100 |
| commit | 7e5873d3755c791e9e4ad2e189164575c978e01c (patch) | |
| tree | d8bebd4622fb5389e05a4220e1c19e5e64d63174 /arch/mips/ralink/Kconfig | |
| parent | MIPS: ralink: Add a few missing clocks (diff) | |
| download | linux-7e5873d3755c791e9e4ad2e189164575c978e01c.tar.xz linux-7e5873d3755c791e9e4ad2e189164575c978e01c.zip | |
MIPS: pci: Add MT7620a PCIE driver
The "a" version of the MT7620 has single port PCIE bus. The driver is
straightforward without any special magic required. The driver works on
MT7620 and MT7628. There are a few magic values that get written to the
pcie phy and a register of which we only know the name. I marked these
places as vodoo in the comments above the code.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11996/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink/Kconfig')
| -rw-r--r-- | arch/mips/ralink/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 016d26e3475a..813826a456ca 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -38,6 +38,7 @@ choice config SOC_MT7620 bool "MT7620/8" + select HW_HAS_PCI config SOC_MT7621 bool "MT7621" |