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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-20 04:07:12 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-20 04:07:12 +0200 |
| commit | 25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (patch) | |
| tree | e0977d906193eadeafebc442775491b844be79d5 /arch/mips/sibyte/sb1250/irq.c | |
| parent | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rol... (diff) | |
| parent | [MIPS] Make timer interrupt frequency configurable from kconfig. (diff) | |
| download | linux-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.tar.xz linux-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.zip | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits)
[MIPS] Make timer interrupt frequency configurable from kconfig.
[MIPS] Correct HAL2 Kconfig description
[MIPS] Fix R4K cache macro names
[MIPS] Add Missing R4K Cache Macros to IP27 & IP32
[MIPS] Support for the RM9000-based Basler eXcite smart camera platform.
[MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board
[MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors.
[MIPS] SN: include asm/sn/types.h for nasid_t.
[MIPS] Random fixes for sb1250
[MIPS] Fix bcm1480 compile
[MIPS] Remove support for NEC DDB5476.
[MIPS] Remove support for NEC DDB5074.
[MIPS] Cleanup memory managment initialization.
[MIPS] SN: Declare bridge_pci_ops.
[MIPS] Remove unused function alloc_pci_controller.
[MIPS] IP27: Extract pci_ops into separate file.
[MIPS] IP27: Use symbolic constants instead of magic numbers.
[MIPS] vr41xx: remove unnecessay items from vr41xx/Kconfig.
[MIPS] IP27: Cleanup N/M mode configuration.
[MIPS] IP27: Throw away old unused hacks.
...
Diffstat (limited to 'arch/mips/sibyte/sb1250/irq.c')
| -rw-r--r-- | arch/mips/sibyte/sb1250/irq.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 0f6e54db4888..f853c32f60a0 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -435,13 +435,17 @@ static inline int dclz(unsigned long long x) return lz; } +extern void sb1250_timer_interrupt(struct pt_regs *regs); +extern void sb1250_mailbox_interrupt(struct pt_regs *regs); +extern void sb1250_kgdb_interrupt(struct pt_regs *regs); + asmlinkage void plat_irq_dispatch(struct pt_regs *regs) { unsigned int pending; #ifdef CONFIG_SIBYTE_SB1250_PROF /* Set compare to count to silence count/compare timer interrupts */ - write_c0_count(read_c0_count()); + write_c0_compare(read_c0_count()); #endif /* @@ -482,7 +486,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) * Default...we've hit an IP[2] interrupt, which means we've * got to check the 1250 interrupt registers to figure out what * to do. Need to detect which CPU we're on, now that - ~ smp_affinity is supported. + * smp_affinity is supported. */ mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), R_IMR_INTERRUPT_STATUS_BASE))); |