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| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2008-08-19 15:55:09 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-10-11 17:18:42 +0200 |
| commit | d10e025f0e4ba4b96d7b5786d232ac5b0b232b11 (patch) | |
| tree | a417a55071b4b7edc22b7c5bb1a2352e7b5986d9 /arch/mips/txx9/rbtx4927 | |
| parent | MIPS: TXx9: Early command-line preprocessing (diff) | |
| download | linux-d10e025f0e4ba4b96d7b5786d232ac5b0b232b11.tar.xz linux-d10e025f0e4ba4b96d7b5786d232ac5b0b232b11.zip | |
MIPS: TXx9: Cache fixup
TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options
to control them. This is useful to debug some cache-related issues,
such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/rbtx4927')
| -rw-r--r-- | arch/mips/txx9/rbtx4927/setup.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 5985f330838a..0464a39b39ac 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -186,14 +186,8 @@ static void __init rbtx4937_clock_init(void); static void __init rbtx4927_mem_setup(void) { - u32 cp0_config; char *argptr; - /* enable caches -- HCP5 does this, pmon does not */ - cp0_config = read_c0_config(); - cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); - write_c0_config(cp0_config); - if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); |