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authorLinus Torvalds <torvalds@linux-foundation.org>2017-05-08 21:32:00 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2017-05-08 21:32:00 +0200
commit9c6ee01ed5bb1ee489d580eaa60d7eb5a8ede336 (patch)
tree6c5286d05ab25310081470ef37fad2e576292679 /arch/mips/xilfpga
parentMerge tag 'xtensa-20170507' of git://github.com/jcmvbkbc/linux-xtensa (diff)
parentMerge branches 'fixes' and 'misc' into for-next (diff)
downloadlinux-9c6ee01ed5bb1ee489d580eaa60d7eb5a8ede336.tar.xz
linux-9c6ee01ed5bb1ee489d580eaa60d7eb5a8ede336.zip
Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King: "Lots of little things this time: - allow modules to be autoloaded according to the HWCAP feature bits (used primarily for crypto modules) - split module core and init PLT sections, since the core code and init code could be placed far apart, and the PLT sections need to be local to the code block. - three patches from Chris Brandt to allow Cortex-A9 L2 cache optimisations to be disabled where a SoC didn't wire up the out of band signals. - NoMMU compliance fixes, avoiding corruption of vector table which is not being used at this point, and avoiding possible register state corruption when switching mode. - fixmap memory attribute compliance update. - remove unnecessary locking from update_sections_early() - ftrace fix for DEBUG_RODATA with !FRAME_POINTER" * 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8672/1: mm: remove tasklist locking from update_sections_early() ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 call ARM: 8668/1: ftrace: Fix dynamic ftrace with DEBUG_RODATA and !FRAME_POINTER ARM: 8667/3: Fix memory attribute inconsistencies when using fixmap ARM: 8663/1: wire up HWCAP/HWCAP2 feature bits to the CPU modalias ARM: 8666/1: mm: dump: Add domain to output ARM: 8662/1: module: split core and init PLT sections ARM: 8661/1: dts: r7s72100: add l2 cache ARM: 8660/1: shmobile: r7s72100: Enable L2 cache ARM: 8659/1: l2c: allow CA9 optimizations to be disabled
Diffstat (limited to 'arch/mips/xilfpga')
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