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| author | Catalin Marinas <catalin.marinas@arm.com> | 2011-03-29 12:40:06 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-10 19:15:24 +0200 |
| commit | f8bec75acdadd3a6597fe0acb5c3161b71cc2ea0 (patch) | |
| tree | 3a81e1641c472bcaca63f7d10824a66b85ad1a0b /arch/mips | |
| parent | MIPS: MSP: Fix build error (diff) | |
| download | linux-f8bec75acdadd3a6597fe0acb5c3161b71cc2ea0.tar.xz linux-f8bec75acdadd3a6597fe0acb5c3161b71cc2ea0.zip | |
MIPS: Rename .data..mostly and properly handle it in linker script
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/cache.h | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/vmlinux.lds.S | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 650ac9ba734c..b4db69fbc40c 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -17,6 +17,6 @@ #define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #endif /* _ASM_CACHE_H */ diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 832afbb87588..e4b0b0bec039 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -74,6 +74,7 @@ SECTIONS INIT_TASK_DATA(PAGE_SIZE) NOSAVE_DATA CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) + READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) DATA_DATA CONSTRUCTORS } |