diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2010-10-08 01:03:43 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 20:08:35 +0200 |
| commit | 1584d7f2d58999c00066a4afc4ad95e07b2a04e8 (patch) | |
| tree | cb451b435fb164ca6582a18a214643329adf87cc /arch/mips | |
| parent | MIPS: Octeon: Update L2 Cache code for CN63XX (diff) | |
| download | linux-1584d7f2d58999c00066a4afc4ad95e07b2a04e8.tar.xz linux-1584d7f2d58999c00066a4afc4ad95e07b2a04e8.zip | |
MIPS: Add identifiers for Octeon II CPUs.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1662/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index b201a8f5b127..049a189ea91f 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -131,6 +131,7 @@ #define PRID_IMP_CAVIUM_CN56XX 0x0400 #define PRID_IMP_CAVIUM_CN50XX 0x0600 #define PRID_IMP_CAVIUM_CN52XX 0x0700 +#define PRID_IMP_CAVIUM_CN63XX 0x9000 /* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC @@ -231,7 +232,7 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, + CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_LAST }; |