diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-03-03 19:48:48 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-10 15:41:46 +0200 |
| commit | 518222161d4a2d3f3b2700098563b62383f83878 (patch) | |
| tree | 61f8ec2c4a6b7f1e5a455106c4b1067bc744fd54 /arch/mips | |
| parent | MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes (diff) | |
| download | linux-518222161d4a2d3f3b2700098563b62383f83878.tar.xz linux-518222161d4a2d3f3b2700098563b62383f83878.zip | |
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction
with "addiu") replaced the "sub" instruction with addiu but it did
not update the immediate value in the R10000_LLSC_WAR case.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9385/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/spinlock.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index b4548690ade9..1fca2e0793dc 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) if (R10000_LLSC_WAR) { __asm__ __volatile__( "1: ll %1, %2 # arch_read_unlock \n" - " addiu %1, 1 \n" + " addiu %1, -1 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |