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authorDavid Daney <ddaney@caviumnetworks.com>2010-10-08 01:03:45 +0200
committerRalf Baechle <ralf@linux-mips.org>2010-10-29 20:08:37 +0200
commit0e56b3852b1c3be83d1f07a82a86084fabacf789 (patch)
tree3120f4ae30ef5933dc0bc9bf4c9f30ff29a155d6 /arch/mips
parentMIPS: Octeon: Handle Octeon II caches. (diff)
downloadlinux-0e56b3852b1c3be83d1f07a82a86084fabacf789.tar.xz
linux-0e56b3852b1c3be83d1f07a82a86084fabacf789.zip
MIPS: Octeon: Probe for Octeon II CPUs.
The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/cpu-probe.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b1b304ea2128..b9378cd0ce0d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
case CPU_BCM6358:
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
+ case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
cpu_wait = r4k_wait;
break;
@@ -953,6 +954,12 @@ platform:
if (cpu == 0)
__elf_platform = "octeon";
break;
+ case PRID_IMP_CAVIUM_CN63XX:
+ c->cputype = CPU_CAVIUM_OCTEON2;
+ __cpu_name[cpu] = "Cavium Octeon II";
+ if (cpu == 0)
+ __elf_platform = "octeon2";
+ break;
default:
printk(KERN_INFO "Unknown Octeon chip!\n");
c->cputype = CPU_UNKNOWN;