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authorPaul Burton <paul.burton@mips.com>2019-09-19 00:03:27 +0200
committerPaul Burton <paul.burton@mips.com>2019-09-20 23:55:07 +0200
commitd1af2ab36d80fcdc15dcaaead68f15352778aec7 (patch)
treef5666df782f272e045396afdd5eb9718d6275483 /arch/mips
parentMIPS: ralink: deactivate PCI support for SOC_MT7621 (diff)
downloadlinux-d1af2ab36d80fcdc15dcaaead68f15352778aec7.tar.xz
linux-d1af2ab36d80fcdc15dcaaead68f15352778aec7.zip
MIPS: Disable pte_special() for MIPS32 with RiXi
Commit 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support") added a _PAGE_SPECIAL bit to the pgprot bits of our PTEs. Unfortunately for MIPS32 configurations with RiXi support this pushed the number of pgprot bits to 13. Since the PFN field in EntryLo begins at bit 12 this results in us shifting the most significant bit of the physical address beyond the end of the PTE, leading any mapped access to a physical address above 2GB to incorrectly access an address 2GB lower than intended. For now, disable the pte_special() support for MIPS32 configurations that support RiXi. Fixes: 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support") Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Dmitry Korotin <dkorotin@wavecomp.com> Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig2
-rw-r--r--arch/mips/include/asm/pgtable-bits.h14
2 files changed, 14 insertions, 2 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3f18aa018a0c..2f7c050e8cde 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -84,7 +84,7 @@ config MIPS
select RTC_LIB
select SYSCTL_EXCEPTION_TRACE
select VIRT_TO_BUS
- select ARCH_HAS_PTE_SPECIAL
+ select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
menu "Machine selection"
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 409ae01ed7be..4da79b85c179 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -52,7 +52,9 @@ enum pgtable_bits {
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
+#endif
};
/*
@@ -79,7 +81,9 @@ enum pgtable_bits {
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
+#endif
};
#elif defined(CONFIG_CPU_R3K_TLB)
@@ -92,7 +96,9 @@ enum pgtable_bits {
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
+#endif
/* Used by TLB hardware (placed in EntryLo) */
_PAGE_GLOBAL_SHIFT = 8,
@@ -116,7 +122,9 @@ enum pgtable_bits {
#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
_PAGE_HUGE_SHIFT,
#endif
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
+#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_CPU_HAS_RIXI)
@@ -139,7 +147,11 @@ enum pgtable_bits {
#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
# define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
#endif
-#define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT)
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+# define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT)
+#else
+# define _PAGE_SPECIAL 0
+#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_XPA)