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| author | Kevin Cernekee <cernekee@gmail.com> | 2009-09-19 04:12:45 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-09-30 21:47:00 +0200 |
| commit | 96983ffefce46312e9372d357309dda413553009 (patch) | |
| tree | da15ecb8a3c728af409fa0903f292731c358e222 /arch/mips | |
| parent | MIPS: Sibyte: Fix compilation error. (diff) | |
| download | linux-96983ffefce46312e9372d357309dda413553009.tar.xz linux-96983ffefce46312e9372d357309dda413553009.zip | |
MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.
This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index b55c2d1b998f..5ab5fa8c1d82 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size) */ static void mips_sc_inv(unsigned long addr, unsigned long size) { + unsigned long lsize = cpu_scache_line_size(); + unsigned long almask = ~(lsize - 1); + + cache_op(Hit_Writeback_Inv_SD, addr & almask); + cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask); blast_inv_scache_range(addr, addr + size); } |