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| author | Jayachandran C <jayachandranc@netlogicmicro.com> | 2011-05-06 22:06:21 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 10:55:40 +0200 |
| commit | efa0f81c11021c95b1e72c65868115b6fb4ecc6a (patch) | |
| tree | 493e0d3db7107e3aafc66bb44f8d5df751395e33 /arch/mips | |
| parent | MIPS: Netlogic: mach-netlogic include files (diff) | |
| download | linux-efa0f81c11021c95b1e72c65868115b6fb4ecc6a.tar.xz linux-efa0f81c11021c95b1e72c65868115b6fb4ecc6a.zip | |
MIPS: Netlogic: Cache, TLB support and feature overrides for XLR
CPU_XLR case added to mm/tlbex.c
CPU_XLR case added to mm/c-r4k.c for PINDEX attribute
Feature overrides for XLR cpu.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2333/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/module.h | 2 | ||||
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
3 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a3eafb..bc01a02cacd8 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71bddf8f7d25..d9bc5d3593b6 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void) case CPU_25KF: case CPU_SB1: case CPU_SB1A: + case CPU_XLR: c->dcache.flags |= MIPS_CACHE_PINDEX; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f5734c2c8097..424ed4b92e6d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; |