diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-04-21 13:25:38 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:30:25 +0200 |
| commit | e70ac023f9515c70cf2b291a294f0f250df29847 (patch) | |
| tree | 9548c871ba43f1022cfc06216f1d9b5609f85905 /arch/mips | |
| parent | MIPS: ptrace: Prevent writes to read-only FCSR bits (diff) | |
| download | linux-e70ac023f9515c70cf2b291a294f0f250df29847.tar.xz linux-e70ac023f9515c70cf2b291a294f0f250df29847.zip | |
MIPS: Allow emulation for unaligned [LS]DXC1 instructions
If an address error exception occurs for a LDXC1 or SDXC1 instruction,
within the cop1x opcode space, allow it to be passed through to the FPU
emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
be handled in a manner consistent with the more common LDC1 & SDC1
instructions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/unaligned.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 5c62065cbf22..28b3af73a17b 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -1191,6 +1191,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, case ldc1_op: case swc1_op: case sdc1_op: + case cop1x_op: die_if_kernel("Unaligned FP access in kernel code", regs); BUG_ON(!used_math()); |