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| author | Sinan Kaya <okaya@codeaurora.org> | 2018-04-03 14:55:03 +0200 |
|---|---|---|
| committer | James Hogan <jhogan@kernel.org> | 2018-04-13 00:01:58 +0200 |
| commit | f6b7aeee8f167409195fbf1364d02988fecad1d0 (patch) | |
| tree | fd7a5652e201f2a401ffdf57973f2e100a507fb1 /arch/mips | |
| parent | MIPS: BCM47XX: Use standard reset button for Luxul XWR-1750 (diff) | |
| download | linux-f6b7aeee8f167409195fbf1364d02988fecad1d0.tar.xz linux-f6b7aeee8f167409195fbf1364d02988fecad1d0.zip | |
MIPS: io: Prevent compiler reordering writeX()
writeX() has strong ordering semantics with respect to memory updates.
In the absence of a write barrier or a compiler barrier, the compiler
can reorder register and memory update instructions. This breaks the
writeX() API.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18997/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/io.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 0cbf3af37eca..fd00ddafb425 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr) #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT) #define war_io_reorder_wmb() wmb() #else -#define war_io_reorder_wmb() do { } while (0) +#define war_io_reorder_wmb() barrier() #endif #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ |