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| author | Akira Takeuchi <takeuchi.akr@jp.panasonic.com> | 2010-10-27 18:28:49 +0200 |
|---|---|---|
| committer | David Howells <dhowells@redhat.com> | 2010-10-27 18:28:49 +0200 |
| commit | a9bc60ebfd5766ce5f6095d0fed3d9978990122f (patch) | |
| tree | d6044bbb56bbb06fb6f13fab9f079a20938d0960 /arch/mn10300/include/asm/tlbflush.h | |
| parent | MN10300: Rename __flush_tlb*() to local_flush_tlb*() (diff) | |
| download | linux-a9bc60ebfd5766ce5f6095d0fed3d9978990122f.tar.xz linux-a9bc60ebfd5766ce5f6095d0fed3d9978990122f.zip | |
MN10300: Make the use of PIDR to mark TLB entries controllable
Make controllable the use of the PIDR register to mark TLB entries as belonging
to particular processes.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/mn10300/include/asm/tlbflush.h')
| -rw-r--r-- | arch/mn10300/include/asm/tlbflush.h | 43 |
1 files changed, 40 insertions, 3 deletions
diff --git a/arch/mn10300/include/asm/tlbflush.h b/arch/mn10300/include/asm/tlbflush.h index 5d54bf57e6c3..c3c194d4031e 100644 --- a/arch/mn10300/include/asm/tlbflush.h +++ b/arch/mn10300/include/asm/tlbflush.h @@ -13,6 +13,12 @@ #include <asm/processor.h> +struct tlb_state { + struct mm_struct *active_mm; + int state; +}; +DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate); + /** * local_flush_tlb - Flush the current MM's entries from the local CPU's TLBs */ @@ -31,20 +37,51 @@ static inline void local_flush_tlb(void) /** * local_flush_tlb_all - Flush all entries from the local CPU's TLBs */ -#define local_flush_tlb_all() local_flush_tlb() +static inline void local_flush_tlb_all(void) +{ + local_flush_tlb(); +} /** * local_flush_tlb_one - Flush one entry from the local CPU's TLBs */ -#define local_flush_tlb_one(addr) local_flush_tlb() +static inline void local_flush_tlb_one(unsigned long addr) +{ + local_flush_tlb(); +} /** * local_flush_tlb_page - Flush a page's entry from the local CPU's TLBs * @mm: The MM to flush for * @addr: The address of the target page in RAM (not its page struct) */ -extern void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr); +static inline +void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr) +{ + unsigned long pteu, flags, cnx; + + addr &= PAGE_MASK; + local_irq_save(flags); + + cnx = 1; +#ifdef CONFIG_MN10300_TLB_USE_PIDR + cnx = mm->context.tlbpid[smp_processor_id()]; +#endif + if (cnx) { + pteu = addr; +#ifdef CONFIG_MN10300_TLB_USE_PIDR + pteu |= cnx & xPTEU_PID; +#endif + IPTEU = pteu; + DPTEU = pteu; + if (IPTEL & xPTEL_V) + IPTEL = 0; + if (DPTEL & xPTEL_V) + DPTEL = 0; + } + local_irq_restore(flags); +} /* * TLB flushing: |