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authorChris Dearman <chris@mips.com>2006-05-08 19:02:16 +0200
committerRalf Baechle <ralf@linux-mips.org>2008-03-12 15:14:40 +0100
commit1f5826bd0ed6c0abec3da28dfffb8d12f0c2cb81 (patch)
tree734b934e846b902faf7d10d4ae104b27956eaeb0 /arch/mn10300
parent[MIPS] Alchemy: Fix ids in Alchemy db dma device table (diff)
downloadlinux-1f5826bd0ed6c0abec3da28dfffb8d12f0c2cb81.tar.xz
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[MIPS] Added missing cases for rdhwr emulation
Some of these are architecturally required for R2 processors so lets try to be bit closer to the real thing. This also provides access to the CPU cycle timer, even on multiprocessors. In that aspect its currently bug compatible to what would happen on a R2-based SMP. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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