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| author | Masanari Iida <standby24x7@gmail.com> | 2019-08-14 05:45:21 +0200 |
|---|---|---|
| committer | Greentime Hu <greentime.hu@sifive.com> | 2019-11-21 09:05:07 +0100 |
| commit | 1b78375c3789cb89912e4a5a47070841211888af (patch) | |
| tree | 592c83e41188ac3791c06233a81cdd26d44a4b13 /arch/nds32 | |
| parent | nds32: remove unneeded clean-files for DTB (diff) | |
| download | linux-1b78375c3789cb89912e4a5a47070841211888af.tar.xz linux-1b78375c3789cb89912e4a5a47070841211888af.zip | |
nds32: Fix typo in Kconfig.cpu
This patch fixes some spelling typo in Kconfig.cpu
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Greentime Hu <green.hu@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Diffstat (limited to 'arch/nds32')
| -rw-r--r-- | arch/nds32/Kconfig.cpu | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu index f80a4ab63da2..f88a12fdf0f3 100644 --- a/arch/nds32/Kconfig.cpu +++ b/arch/nds32/Kconfig.cpu @@ -13,7 +13,7 @@ config FPU default n help If FPU ISA is used in user space, this configuration shall be Y to - enable required support in kerenl such as fpu context switch and + enable required support in kernel such as fpu context switch and fpu exception handler. If no FPU ISA is used in user space, say N. @@ -27,7 +27,7 @@ config LAZY_FPU enhance system performance by reducing the context switch frequency of the FPU register. - For nomal case, say Y. + For normal case, say Y. config SUPPORT_DENORMAL_ARITHMETIC bool "Denormal arithmetic support" @@ -36,7 +36,7 @@ config SUPPORT_DENORMAL_ARITHMETIC help Say Y here to enable arithmetic of denormalized number. Enabling this feature can enhance the precision for tininess number. - However, performance loss in float pointe calculations is + However, performance loss in float point calculations is possibly significant due to additional FPU exception. If the calculated tolerance for tininess number is not critical, @@ -73,7 +73,7 @@ choice the cache aliasing issue. The rest cpus(N13, N10 and D10) are implemented as VIPT data cache. It may cause the cache aliasing issue if its cache way size is larger than page size. You can specify the - CPU type direcly or choose CPU_V3 if unsure. + CPU type directly or choose CPU_V3 if unsure. A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. A kernel built for N15 is able to run on N15 or D15. |