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authorPaul Walmsley <paul.walmsley@sifive.com>2019-10-11 00:57:58 +0200
committerPaul Walmsley <paul.walmsley@sifive.com>2019-10-14 21:35:36 +0200
commit4c8eb19cf9dc5fcc489757acbf93be90baf25848 (patch)
treee0c65f24364f91e5e363e6ac3b568871041711cc /arch/nios2
parentriscv: dts: HiFive Unleashed: add default chosen/stdout-path (diff)
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riscv: tlbflush: remove confusing comment on local_flush_tlb_all()
Remove a confusing comment on our local_flush_tlb_all() implementation. Per an internal discussion with Andrew, while it's true that the fence.i is not necessary, it's not the case that an sfence.vma implies a fence.i. We also drop the section about "flush[ing] the entire local TLB" to better align with the language in section 4.2.1 "Supervisor Memory-Management Fence Instruction" of the RISC-V Privileged Specification v20190608. Fixes: c901e45a999a1 ("RISC-V: `sfence.vma` orderes the instruction cache") Reported-by: Alan Kao <alankao@andestech.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Andrew Waterman <andrew@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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