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| author | Stafford Horne <shorne@gmail.com> | 2017-10-30 13:38:35 +0100 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-11-03 06:01:13 +0100 |
| commit | 9b54470afd836278a7e6f0f08194e2e2dca4b6eb (patch) | |
| tree | 5471b19b526dd33b375f2ce7b129fce5f226a794 /arch/openrisc/Kconfig | |
| parent | dt-bindings: add openrisc to vendor prefixes list (diff) | |
| download | linux-9b54470afd836278a7e6f0f08194e2e2dca4b6eb.tar.xz linux-9b54470afd836278a7e6f0f08194e2e2dca4b6eb.zip | |
irqchip: add initial support for ompic
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
architecture specification:
https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing. This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/Kconfig')
| -rw-r--r-- | arch/openrisc/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index b49acda5e8f4..34eb4e90f56c 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool y |