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| author | Stafford Horne <shorne@gmail.com> | 2017-07-06 23:06:30 +0200 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-11-03 06:01:16 +0100 |
| commit | 4553474d977d1ee8a81067cfbc588f1df84ce3e9 (patch) | |
| tree | 4e74260eb9134fd94a7bc20fc3ab23e4ecb3a7e1 /arch/openrisc/kernel/Makefile | |
| parent | openrisc: enable LOCKDEP_SUPPORT and irqflags tracing (diff) | |
| download | linux-4553474d977d1ee8a81067cfbc588f1df84ce3e9.tar.xz linux-4553474d977d1ee8a81067cfbc588f1df84ce3e9.zip | |
openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/kernel/Makefile')
| -rw-r--r-- | arch/openrisc/kernel/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index b4b51a07016a..9028e5a1fdd7 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -8,7 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o unwinder.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SMP) += smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o |