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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-08-06 12:45:42 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-08-06 12:45:42 +0200 |
| commit | 9e90c7985229430428dc9ba0ec7fe422901b456d (patch) | |
| tree | cae2072feba8cc433a32d96568bbcf36070bd6e5 /arch/openrisc/kernel/entry.S | |
| parent | genirq/irqchip: Remove MULTI_IRQ_HANDLER as it's now obselete (diff) | |
| parent | irqchip/gic-v3-its: Make its_lock a raw_spin_lock_t (diff) | |
| download | linux-9e90c7985229430428dc9ba0ec7fe422901b456d.tar.xz linux-9e90c7985229430428dc9ba0ec7fe422901b456d.zip | |
Merge tag 'irqchip-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:
- GICv3 ITS LPI allocation revamp
- GICv3 support for hypervisor-enforced LPI range
- GICv3 ITS conversion to raw spinlock
Diffstat (limited to 'arch/openrisc/kernel/entry.S')
| -rw-r--r-- | arch/openrisc/kernel/entry.S | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index 690d55272ba6..0c826ad6e994 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -277,12 +277,6 @@ EXCEPTION_ENTRY(_data_page_fault_handler) l.addi r3,r1,0 // pt_regs /* r4 set be EXCEPTION_HANDLE */ // effective address of fault - /* - * __PHX__: TODO - * - * all this can be written much simpler. look at - * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part - */ #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX l.lwz r6,PT_PC(r3) // address of an offending insn l.lwz r6,0(r6) // instruction that caused pf @@ -314,7 +308,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler) #else - l.lwz r6,PT_SR(r3) // SR + l.mfspr r6,r0,SPR_SR // SR l.andi r6,r6,SPR_SR_DSX // check for delay slot exception l.sfne r6,r0 // exception happened in delay slot l.bnf 7f |