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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-27 04:46:23 +0100 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-27 04:46:23 +0100 |
commit | a9a07d40bc9c57881555b64fe8bf66fd28e2f13a (patch) | |
tree | 20c08b4e6756db92bf7720d5ca1af67b83430828 /arch/openrisc/mm/init.c | |
parent | Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/ker... (diff) | |
parent | openrisc: add missing header inclusion (diff) | |
download | linux-a9a07d40bc9c57881555b64fe8bf66fd28e2f13a.tar.xz linux-a9a07d40bc9c57881555b64fe8bf66fd28e2f13a.zip |
Merge branch 'for-upstream' of git://openrisc.net/jonas/linux
Pull OpenRISC updates from Jonas Bonn:
"An equal number of bug fixes and trivial cleanups; no new features.
- Two patches to fix errors thrown by the updated toolchain.
- Three other bug fixes.
- Four trivial cleanups."
* 'for-upstream' of git://openrisc.net/jonas/linux:
openrisc: add missing header inclusion
openrisc: really pass correct arg to schedule_tail
Add bitops include needed for ext2 filesystem
openrisc: update DTLB-miss handler last
openrisc: fix up vmalloc page table loading
openrisc idle: delete pm_idle
openrisc: remove CONFIG_SYMBOL_PREFIX
openrisc: avoid using function parameter regs in reset vector
openrisc: remove unused current_regs
Diffstat (limited to 'arch/openrisc/mm/init.c')
-rw-r--r-- | arch/openrisc/mm/init.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index 79dea9740a3c..e7fdc50c4bf0 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -167,15 +167,26 @@ void __init paging_init(void) unsigned long *dtlb_vector = __va(0x900); unsigned long *itlb_vector = __va(0xa00); + printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler); + *itlb_vector = ((unsigned long)&itlb_miss_handler - + (unsigned long)itlb_vector) >> 2; + + /* Soft ordering constraint to ensure that dtlb_vector is + * the last thing updated + */ + barrier(); + printk(KERN_INFO "dtlb_miss_handler %p\n", &dtlb_miss_handler); *dtlb_vector = ((unsigned long)&dtlb_miss_handler - (unsigned long)dtlb_vector) >> 2; - printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler); - *itlb_vector = ((unsigned long)&itlb_miss_handler - - (unsigned long)itlb_vector) >> 2; } + /* Soft ordering constraint to ensure that cache invalidation and + * TLB flush really happen _after_ code has been modified. + */ + barrier(); + /* Invalidate instruction caches after code modification */ mtspr(SPR_ICBIR, 0x900); mtspr(SPR_ICBIR, 0xa00); |