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| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | 2015-05-01 01:14:11 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2015-05-01 05:52:09 +0200 |
| commit | 1ae79b78bc52b910a224f3795122538516e07b5f (patch) | |
| tree | d934d597c7c63219901eec7ab644d960ed48b7a7 /arch/parisc/oprofile | |
| parent | powerpc/pseries: Correct cpu affinity for dlpar added cpus (diff) | |
| download | linux-1ae79b78bc52b910a224f3795122538516e07b5f.tar.xz linux-1ae79b78bc52b910a224f3795122538516e07b5f.zip | |
powerpc/eeh: Fix race condition in pcibios_set_pcie_reset_state()
When asserting reset in pcibios_set_pcie_reset_state(), the PE
is enforced to (hardware) frozen state in order to drop unexpected
PCI transactions (except PCI config read/write) automatically by
hardware during reset, which would cause recursive EEH error.
However, the (software) frozen state EEH_PE_ISOLATED is missed.
When users get 0xFF from PCI config or MMIO read, EEH_PE_ISOLATED
is set in PE state retrival backend. Unfortunately, nobody (the
reset handler or the EEH recovery functinality in host) will clear
EEH_PE_ISOLATED when the PE has been passed through to guest.
The patch sets and clears EEH_PE_ISOLATED properly during reset
in function pcibios_set_pcie_reset_state() to fix the issue.
Fixes: 28158cd ("Enhance pcibios_set_pcie_reset_state()")
Reported-by: Carol L. Soto <clsoto@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Tested-by: Carol L. Soto <clsoto@us.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/parisc/oprofile')
0 files changed, 0 insertions, 0 deletions